Tipping the Scales: An Electronic Design FAQ on 3D Flash Memory Density Scaling

3D Flash Memory Density Scaling

The flash memory landscape is full of notable milestones, and the shift from traditional 2D planar NAND to 3D – where memory cells are stacked vertically in multiple layers – is one of the most significant.

Over a decade ago, KIOXIA researchers produced a paper that outlined the concept of a three-dimensional memory cell, one that made it possible to stack cells vertically in multiple layers rather than flat on the silicon surface. This novel approach has driven significant capacity increases and lowered cost per bit. It has addressed the memory and storage demands of virtually all of today's disruptive technologies— including the cloud, big data, IoT, predictive analytics and so on.

It has also caused designers to make adjustments.

Working with Electronic Design’s Bill Wong, we put together a list of the most frequently asked questions application designers have when it comes to working with 3D stacks.


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The views and opinions expressed in this blog are those of the author(s) and do not necessarily reflect those of KIOXIA America, Inc.

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